The present invention relates to a technique for carrying out processing using a plurality of hardware processing modules and, in particular, to a data processing device that carries out processing by operating a plurality of hardware processing modules in parallel.
Recently, manufacturers of data processing devices such as wireless communication devices and computers pursue enhancing and diversifying the functions of these devices. Especially, in the fields of communication, image processing, image recognition, etc., such devices are often equipped with media processing engines by which diverse kinds of media processing are implemented. There are wide-ranging requirements for such media processing engines that are implemented with semiconductor technology.
For example, there is an increasing need for a media processing engine that is capable of processing a huge amount of media data in real time. It would be impossible to achieve such a need by relying on only the processing capability of a single CPU (Central Processing Unit), DSP (Digital Signal Processor), etc.
There are also increasing needs for battery drive performance for use in mobile environment and for low power consumption in terms of countermeasures against heat generation.
In addition, with evolution of semiconductor processes, the cost for development of SoC (System on a Chip) rises. This leads to growing demands to decrease the types of semiconductor chips to be developed and to allow a single semiconductor chip to support a plurality of applications. Since customer requirements on marketed products (final products) change rapidly, the cycle of developing a new product (final product) to be marketed needs to be shorter. Consequently, for semiconductor chips, it is also required to shorten the time-to-market.
In the field of communication, particularly, wireless communication including broadcast equipment and mobile phones, and in the field of image processing or the like entailing compression/decompression, diversified standards have been established worldwide and these standards continue to be updated incessantly toward the next generation. To implement multimode processing engines conformable to these standards, semiconductor chips for this purpose are required to have high programmability and high scalability.
Furthermore, developing software is important for semiconductor chips having programmability. In the software development as well, high performance, high quality, and a short delivery period are required and there is a growing demand for the easiness to develop software in order to achieve these requirements.
As techniques relating to the above issues, there are inventions disclosed in the following patent documents 1 to 4. Patent document 1 is intended to solve a problem that latency occurs depending on scheduling in a parallel operational processing device in which processes that can be executed by operation units are fixed. The parallel operational processing device comprises an external input means, a stream input/output means, an external output means, a bus network, an application specific processing circuit, a plurality of operation units, a selector that selects one of first to third clocks, and a control means that adaptively assign, to the plural operation units, processes which comprise external input processing, external output processing, and processing other than the external input processing and the external output processing.
Patent document 2 is intended to provide an image processing apparatus and an image processing method capable of improving the performance of the whole system without adding a receiving buffer or the like, which would result in an increase in the cost. A data packet with a header attached to image data is used. Image processing information is described within the header. When a data packet is input to an image processing LSI, the LSI performs image processing on image data if it is allowed to process the input data packet, and then describes in the header processing complete information indicating that the image processing has finished. If the LSI is not allowed to process the packet, it outputs the packet without describing processing complete information. Thereby, even if an image processing LSI is placed in a state not capable of processing image data, it can transfer a received data packet to the following image processing LSI to hand over the processing to the following LSI. Resources such as image processing LSIs and a bus can be used efficiently.
Patent document 3 is intended to provide a signal processing device and electronic equipment using same, capable of carrying out high-performance and high-efficiency image processing with regard to image processing such as MPEG-4 AVC coding/decoding in which a huge amount of data should be processed. The signal processing device comprises an instruction parallel processor, a first data parallel processor, a second data parallel processor, and application specific hardware that comprises a motion detecting unit, a deblocking filtering unit, and a variable length coding/decoding unit. By this configuration, it is possible to provide a signal processing apparatus and electronic equipment using same, realizing high processing capability and flexibility by distributing load between software and hardware in signal processing of an image compression/decompression algorithm in which a very large amount of data should be processed.
Patent document 4 is intended to provide a multitask processor capable of executing a plurality of tasks in parallel and simultaneously, while suppressing an increase in circuit scale. This multitask processor comprises an instruction memory for storing a program, two instruction processors, each of which reads and decodes an instruction described in a program stored in the instruction memory and executes the instruction as a task, and a scheduler that selects and assigns a task to each of the two instruction processors, based on priority between and among a plurality of tasks.
[Prior Art Documents]
    [Patent Documents]    [Patent Document 1]    Japanese Unexamined Patent Publication No. 2004-326228    [Patent Document 2]    Japanese Unexamined Patent Publication No. 2001-312479    [Patent Document 3]    Japanese Unexamined Patent Publication No. 2005-070938    [Patent Document 4]    Japanese Unexamined Patent Publication No. 2003-323309